1. Field of the Invention
This invention relates to flash memory devices and more particularly to improved design of the silicon oxide dielectric layers above the source region of the devices.
2. Description of Related Art
Flash memory EEPROM (Electrically Erasable Programmable Read Only Memory) devices comprise electrically-erasable, non-volatile memory devices, which are fabricated with tunnel oxides, as well as high voltage transistors, for programming and erasing the devices.
FLOTOX (FLOating-gate Tunneling OXide) EEPROM devices are formed of an MOS transistor with a floating gate formed above a thin gate oxide (tunnel oxide) of from about 80.ANG.-120.ANG. thick near the drain region with a (500.ANG.) 200.ANG. to 500.ANG. thick gate oxide formed elsewhere. Programming of the EEPROM is done by transferring electrons from the substrate to the floating gate electrode through the thin tunnel oxide layer by means of channel hot-electron injection. When programming an EEPROM, the control gate voltage is raised to a high level. For example the control gate voltage is raised to 12 Volts along with a drain voltage of 7 Volts so that channel hot-electron injection occurs in a FLOTOX EEPROM. In EEPROMS in general the floating gate is erased by grounding the control gate electrode and raising the source voltage to 12 Volts to cause discharge of the floating gate electrode by means of Fowler-Nordheim tunneling.
Most flash EEPROM cells have a double polysilicon structure with the upper polysilicon layer patterned to form the control gates and the word lines of the structure. The lower polysilicon layer is patterned to form the floating gates with a gate oxide having a thickness of about 100.ANG. and an interpolysilicon dielectric comprising ONO (silicon dioxide/silicon nitride/silicon dioxide) having a thickness of from about 200.ANG. to about 500.ANG..
FIG. 1 shows a sectional view of a fragment of a prior art EEPROM device 8 which includes a P- doped silicon semiconductor substrate B1 in which an N+ doped drain region D1 and an N+ doped source region S1 have been formed on opposite sides of channel region C1, which lies below a portion of a gate electrode stack ST1. The gate electrode stack ST1 comprises a first gate oxide layer GOX1, a first floating gate electrode polysilicon layer FG1, a first interpolysilicon layer IP1, and a first polysilicon control gate electrode layer CG1.
The process for formation of the structure of FIG. 1 includes the steps as follows:
1. A sacrificial silicon oxide layer is grown on the surface of a P- doped silicon semiconductor substrate to clean the edge of the field oxide (i.e. bird's beak, Kooi effect). The sacrificial silicon oxide layer is then stripped before growth of the tunnel oxide. PA0 2. Form a blanket gate oxide layer GOX1 over P- doped silicon substrate B1. PA0 3. Form a blanket first polysilicon (floating gate electrode) layer FG1 over gate oxide layer GOX1 PA0 4. Form a blanket interpolysilicon ONO layer IP1 over floating gate electrode layer FG1. PA0 5. Form a blanket second polysilicon (control gate electrode) layer CG1 over interpolysilicon layer IP1. PA0 6. Form a photoresist mask and using the mask, etch away unprotected portions of the layers therebelow above the substrate to form the flash memory gate electrode stack ST1 from blanket layers GOX1, FG1, IP1, and CG1. PA0 7. While masking one side of the gate electrode stack, ion implant ions on the other (source region) side of the gate electrode stack ST1, into the P- doped substrate B1 to form the N+ doped source region S1 on the unmasked side of the gate electrode stack ST1. PA0 8. Drive ions into the source region S1 to make source region S1 deep. PA0 9. Implant ions into the substrate B1 to form a more shallow N+ doped drain region D1 on the other side of the gate electrode stack ST1 from the source region. PA0 A. There is an extended thermal cycle that reduces the charge to breakdown Q.sub.BD of tunnel oxide (where Q.sub.BD is an indicator of how many program/erase cycles an EEPROM cell can operate without going into breakdown condition.) PA0 B. It is not possible to tailor source and drain edges of overlap oxide thickness to meet different voltages requirements during program and erase, as follows: PA0 1. Form a doped source region in a surface of a semiconductor substrate, one side of the channel region of the transistor, PA0 2. Form on the surface of the semiconductor substrate a silicon oxide tunnel dielectric layer over a semiconductor substrate for the transistor. PA0 3. When forming the tunnel dielectric layer, form a thicker gate dielectric layer over a portion of the source region because oxidation is faster on the doped source region. PA0 4. Form a floating gate layer, an interelectrode dielectric layer, and a control gate layer over the channel region of the transistor. PA0 5. Form at another side of the gate electrode stack opposite from the source region of the stack a doped drain region in the surface of the substrate of the doped drain region overlapping the gate structure due to lateral diffusion caused by the thermal cycle later on during manufacturing. PA0 1. A surface of a semiconductor substrate has a silicon oxide tunnel dielectric layer formed over a semiconductor substrate. A stacked-gate structure for the transistor comprising a floating gate layer, an interelectrode dielectric layer, and a control gate layer are formed above the tunnel dielectric. PA0 2. A doped source region is formed on one side of the stacked gate structure in the surface of the substrate with one edge of the doped source region overlapping the gate structure. PA0 3. A doped drain region is formed in the surface of the substrate at another side of the stacked gate structure opposite from the one side of the stacked gate structure with one edge of the doped drain region overlapping the gate structure. PA0 4. A thicker gate oxide dielectric layer is formed over a portion of the source region. PA0 5. Accordingly, the tunnelling dielectric layer lies beneath the stacked gate structure, over the substrate and over the drain region.
Problems encountered with the above process of making the device of FIG. 1 are as follows:
Source: 12 V during erase. PA1 Drain: 7 V during program.